| Issue | Title | |||
| No 1 (2016) | SRAM WITH A REDUDANCY CELL GATE ARRAY |
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| Tyurin S.F. | ||||
| No 2 (2016) | FORMAL SYSTEM FOR FAULT-TOLERANT CMOS SELF-TIMED CIRCUITS |
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| Tyurin S.F., Kamenskih A.N. | ||||
| No 19 (2016) | REALIZATION OF 6 INPUT LUT IN ADAPTIVE LOGIC MODULE |
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| Tyurin S.F. | ||||
| No 38 (2021) | PROVIDING HIGH RELIABILITY OF FPGAs FOR CRITICAL APPLICATIONS BASED ON HYBRID REDUNDANCY |
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| Grekov A.V. | ||||
| No 1 (2014) | THE ANALYSIS OF SELF-TIMED FULL-ADDER IN TERMS OF FAULT-TOLERANCE |
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| Tyurin S.F., Kamenskih A.N. | ||||
| No 2 (2015) | TRANSISTOR TREE TO IMPLEMENT SYSTEMS OF LOGIC FUNCTIONS |
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| Tyurin S.F. | ||||
| 1 - 6 of 6 Items | ||||
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