| Issue | Title | 
																												
								| No 8 (2013) | REKONFIGURATsIYa I DIAGNOSTIROVANIE LOGIKI PLIS FPGA |  | 
							
					| Tyurin S.F.,													Gromov O.A.,													Gorodilov A.Y. | 
						
																										
								| No 2 (2015) | TRANSISTOR TREE TO IMPLEMENT SYSTEMS OF LOGIC FUNCTIONS |  | 
							
					| Tyurin S.F. | 
						
																										
								| No 19 (2016) | REALIZATION OF 6 INPUT LUT IN ADAPTIVE LOGIC MODULE |  | 
							
					| Tyurin S.F. | 
						
																										
								| No 1 (2016) | SRAM WITH A REDUDANCY CELL GATE ARRAY |  | 
							
					| Tyurin S.F. | 
						
																										
								| No 24 (2017) | SIMULATION AND OPTIMIZATION OF INNOVATIVE FPGA’s LOGICAL ELEMENTS |  | 
							
					| Vikhorev R.V.,													Prokhorov A.S.,													Tyurin S.F.,													Nikitiin A.S. | 
						
																										
								| No 31 (2019) | DIAGNOSIS OF FPGA WITH NEW ELEMENTS |  | 
							
					| Danilova E.Y. | 
						
																										
								| No 8 (2013) | Kontseptsiya «ZELENOY» LOGIKI |  | 
							
					| Tyurin S.F.,													Plotnikova A.Y. | 
						
																										
								| No 3 (2014) | INCREASING THE RELIABILITY OF THE LUT FPGA OPERATION |  | 
							
					| Tyurin S.F. | 
						
																										
								| No 15 (2015) | AUTOMATIC SYNTHESIS OF COMBINATIONAL CIRCUITS USING QUARTUSII STATE MACHINE EDITOR |  | 
							
					| Tyurin S.F. | 
						
																										
								| Vol 1, No 7 (2013) | SRAVNENIE MODELEY VNEShNIKh OTKAZOV ELEMENTARNOGOMUL'TIPLEKSORA LOGIChESKOGO ELEMENTA PLIS FPGA OTNOSITEL'NO POKRYVAYuShchIKh TESTOVYKh NABOROV |  | 
							
					| Tyurin S.F.,													Ermakov S.V.,													Gorodilov A.Y. | 
						
							
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