Issue |
Title |
No 3 (2014) |
INCREASING THE RELIABILITY OF THE LUT FPGA OPERATION |
|
Tyurin S.F. |
Vol 1, No 7 (2013) |
SRAVNENIE MODELEY VNEShNIKh OTKAZOV ELEMENTARNOGOMUL'TIPLEKSORA LOGIChESKOGO ELEMENTA PLIS FPGA OTNOSITEL'NO POKRYVAYuShchIKh TESTOVYKh NABOROV |
|
Tyurin S.F., Ermakov S.V., Gorodilov A.Y. |
No 38 (2021) |
PROVIDING HIGH RELIABILITY OF FPGAs FOR CRITICAL APPLICATIONS BASED ON HYBRID REDUNDANCY |
|
Grekov A.V. |
No 8 (2013) |
REKONFIGURATsIYa I DIAGNOSTIROVANIE LOGIKI PLIS FPGA |
|
Tyurin S.F., Gromov O.A., Gorodilov A.Y. |
No 40 (2021) |
MATHEMATICAL MODEL OF AN ARTIFICIAL NEURAL NETWORK FOR FPGA DEVICES AND MICROCONTROLLERS FOCUSED ON FOG COMPUTING |
|
Bakhtin V.V. |
No 2 (2015) |
METHOD OF DIAGNOSTIC DIGITAL CIRCUIT WITH PROGRAMMABLE PLD ON PRODUCTION STAGE |
|
Kiselyov V.V., Suvorov N.A. |
No 2 (2015) |
TRANSISTOR TREE TO IMPLEMENT SYSTEMS OF LOGIC FUNCTIONS |
|
Tyurin S.F. |
No 15 (2015) |
AUTOMATIC SYNTHESIS OF COMBINATIONAL CIRCUITS USING QUARTUSII STATE MACHINE EDITOR |
|
Tyurin S.F. |
No 1 (2016) |
SELF-TIMED ELEMENTS AND DEVICES |
|
Bereznyakov S.V., Averkiev M.A. |
No 19 (2016) |
REALIZATION OF 6 INPUT LUT IN ADAPTIVE LOGIC MODULE |
|
Tyurin S.F. |
No 23 (2017) |
FAULT TOLERANT PROGRAMMABLE LOGIC ARRAY |
|
Tyurin S.F., Prokhorov A.S. |
No 24 (2017) |
SIMULATION AND OPTIMIZATION OF INNOVATIVE FPGA’s LOGICAL ELEMENTS |
|
Vikhorev R.V., Prokhorov A.S., Tyurin S.F., Nikitiin A.S. |
No 31 (2019) |
HARDWARE NEURAL NETWORKS PROGRESS ON FPGA AND ASIC |
|
Shipitsin S.P., Iamaev M.I. |
1 - 13 of 13 Items |
|