Tyurin, S. F, Perm National Research Polytechnic University
| Issue | Section | Title | Abstract | File |
| No 24 (2017) | Articles | TECHNIQUE OF A FINITE-STATE MACHINE SEQUENCES SET GENERATOR LAB | Abstract |
 (Rus) |
| No 23 (2017) | Articles | FAULT TOLERANT PROGRAMMABLE LOGIC ARRAY | Abstract |
(Rus) |
| No 23 (2017) | Articles | PROGRAMMABLE LOGIC ELEMENTS OF FPGA FOR REALIZATION SYSTEM OF LOGICAL FUNCTIONS | Abstract |
(Rus) |
| No 22 (2017) | Articles | TECHNIQUE OF A FINITE-STATE MACHINE SEQUENCES SET GENERATOR LAB | Abstract |
(Rus) |
| No 20 (2016) | Articles | THE METHODICAL TECHNIQUE OF THE CONDUCTION OF LABORATORIAL CLASSES ON THE SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE "HARD" LOGIC IN THE QUARTUS II | Abstract |
(Rus) |
| No 19 (2016) | Articles | REALIZATION OF 6 INPUT LUT IN ADAPTIVE LOGIC MODULE | Abstract |
(Rus) |
| No 2 (2016) | Articles | A HANOI TOWER PROBLEM | Abstract |
(Rus) |
| No 2 (2016) | Articles | FORMAL SYSTEM FOR FAULT-TOLERANT CMOS SELF-TIMED CIRCUITS | Abstract |
(Rus) |
| No 1 (2016) | Articles | SRAM WITH A REDUDANCY CELL GATE ARRAY | Abstract |
(Rus) |
| No 4 (2015) | Articles | WEAK MULLER’S C-GATE | Abstract |
(Rus) |
| No 15 (2015) | Articles | AUTOMATIC SYNTHESIS OF COMBINATIONAL CIRCUITS USING QUARTUSII STATE MACHINE EDITOR | Abstract |
(Rus) |
| No 2 (2015) | Articles | TRANSISTOR TREE TO IMPLEMENT SYSTEMS OF LOGIC FUNCTIONS | Abstract |
(Rus) |
| No 1 (2015) | Articles | REVIEW OF TECHNOLOGIES OF GREEN COMPUTING | Abstract |
(Rus) |
| No 4 (2014) | Articles | SIMULATION OF THE RADIATION-STEADY DICE SRAM CELL | Abstract |
(Rus) |
| No 3 (2014) | Articles | INCREASING THE RELIABILITY OF THE LUT FPGA OPERATION | Abstract |
(Rus) |
| No 2 (2014) | Articles | THE PROTECTION OF DIGITAL DEVICE FROM SIGNEL STUCK-AT FAULT USING REDUNDANT TRANSISTOR STRUCTURES | Abstract |
(Rus) |
| No 1 (2014) | Articles | THE ANALYSIS OF SELF-TIMED FULL-ADDER IN TERMS OF FAULT-TOLERANCE | Abstract |
(Rus) |